Generally, demands in semiconductor fabrication technology have focused on obtaining high integration. Accordingly, demands for a post process for forming multi-layer lines in a semiconductor device such as metal lines for connecting devices electrically together after forming transistors, bitlines, capacitors and the like to accomplish a reduction in size, ultra-large size and ultra-high integration of the semiconductor device.
As illustrated in example FIG. 1A, in a metal line fabricating method in a semiconductor device, after a semiconductor device such as a photodiode, a transistor, a capacitor and the like has been formed on and/or over semiconductor substrate 1, protective layer 2 is formed on and/or over semiconductor substrate 1. In example drawing FIG. 1A, a MOS transistor including gate electrode G, source S and drain D is illustrated as a semiconductor device.
As illustrated in example FIG. 1B, the protective layer is selectively removed by photolithography to form contact holes. After barrier metal layer 3 and metal layer (e.g., tungsten layer) 4 have been formed on and/or over protective layer 2 to fill the contact holes, a first contact plug including barrier metal layer 3 and metal layer 4 stacked thereon and/or thereover is formed in each of the contact holes by CMP.
As illustrated in example FIG. 1C, a metal substance for forming a metal line is deposited on and/or over protective layer 2 and is then patterned to form first metal line 5 electrically connected to the first contact plug. Subsequently, first insulating interlayer 6 is formed on and/or over first metal line 5. A surface of first insulating interlayer 6 may be formed uneven due to a step difference of first metal line 5 beneath first insulating interlayer 6. To planarize first insulating interlayer 6, chemical mechanical polishing (CMP) can be performed.
As illustrated in example FIG. 1D, contact holes are formed on and/or over first metal line 5 by selectively removing portions of first insulating interlayer 6 by photolithography. After barrier metal layer 7 and metal layer 8 have been formed on and/or over first insulating interlayer 6 to fill the contact holes formed in first insulating interlayer 6, a second contact plug including barrier metal layer 7 and metal layer 8 stacked thereon and/or thereover is formed in each of the contact holes by CMP. Subsequently, multi-layer metal lines are formed by repeating the above steps illustrated in example FIGS. 1C and 1D.
As mentioned in the above description, in forming the multi-layer metal lines of the semiconductor device, an insulating interlayer is deposited on and/or over a lower metal line, a contact hole is formed by selectively removing the insulating interlayer, a contact plug is formed within the contact hole, and an upper metal line is then formed thereon. However, in case that particles and the like exist on and/or over the insulating interlayer around or on the contact area, the contact hole fails to be formed to expose the lower metal line sufficiently or is formed to partially expose the lower metal line. Therefore, if the contact hole fails to be formed completely, the metal line is open to cause malfunction to the semiconductor device. Moreover, contact resistance is increased to reduce an operational speed of the semiconductor device.